Turnkey environment allows MEMS/IC co-design, co-verification
Posted by coventor marketing on Mon, May 18, 2009 @ 03:02 PM
Coventor partners with Cadence to dovetail MEMS+ 3-D CAD with Virtuoso
R. Colin Johnson EE Times
(05/18/2009 12:01 AM EDT)
PORTLAND, Ore. - Cadence Design Systems Inc. has teamed with Coventor Inc. on what the pair says is the first environment to allow 3-D microelectromechanical system (MEMS) models to be designed and simulated in tandem with CMOS integrated circuitry. MEMS+IC is debuting in Munich Germany, at Cadence's CDNLive EMEA (Europe, Middle East, and Africa) conference, which opens today (May 18).
Traditionally, MEMS chip design requires a separate design effort for a CMOS application-specific integrated circuit (ASIC), whether the two are destined for separate chips or are to be housed on the same die. The MEMS structures are designed using a 3-D computer-aided design (CAD) system, and tedious hand translation of process parameters is required when transferring the MEMS design to a semiconductor circuit simulator and verification tool.
Coventor (Cary, N.C.) worked with Cadence (San Jose, Calif .) to preset its new MEMS+ 3-D CAD offering to dovetail with Cadence's Virtuoso Schematic Editor, allowing automatic translation of all necessary dimensions and process parameters from MEMS+ to Virtuoso. MEMS+IC thus unites the two design efforts, enabling full co-simulation and co-verification.
"MEMS designers have a 3-D environment for creating their MEMS models; then they export all the views and files needed [for] layout in Cadence Virtuoso Schematic Editor," said Joost van Kuijk, vice president of marketing and business development at Coventor. "The models are heavily parameterized, so you can actually do all of the things you need to do over on the Cadence side."
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