MEMS Design Contest

Design Tools

• Cadence tools for designing, implementing, and simulating MEMS and mixed-signal designs will be needed by all contestants.   If they are not available at the contestant's site, they can be purchased through Cadence's regular distribution channels or by contacting Cadence directly.  Dependent on the region and the legal status of the contest participant, the tools may be available through a third party such as Europractice in the EMEA region
  
• Coventor will provide MEMS design software, at no charge, to contestants with an accepted proposal
• After signing an NDA, the participants will gain access to the required PDKs and IP of X-FAB
• All sponsors have the right to decline distribution of tools and PDKs at their sole discretion.
  

Training and Workshops

In order to familiarize design groups with MEMS/mixed-signal co-design, several training courses and workshops will be provided by the organizers:

• Cadence will provide free Internet Learning Series (iLS) training about the basic tool features. These courses are available to the participants online and can be started at any time.   Click here to obtain a list of applicable training courses offered by Cadence.    CADENCE TRAINING COURSES
  
• Coventor will provide reference training material in an online format and will propose online design reviews during the design phase, as well as a design review meeting.

Since the contest is worldwide, all workshops and seminars will be provided as webinars and video recordings. There will be offline workshops and meetings, but the content will become available online soon after the workshops.

• The dates for the workshops will be announced later in the year
• There will be regular monthly worldwide calls, where participants can ask questions of the experts from the sponsor companies

Rapid Adoption Kits (RAKs) recommended to the MEMS Design Contest participants:

Front-end Environment:

• Virtuoso ADE Explorer and Virtuoso ADE Assembler
• Run Plan
• Virtuoso ADE Explorer and Virtuoso ADE Assembler Expression Builder
• Virtuoso ADE Verifier
• Check & Assertions
• Introduction to Device Safe Operating Area ( SOA ) Circuit Conditions & Asserts Workshop
• Analog Design Environment XL (ADE XL) Workshop
• Static and Dynamic Checks
• Basics of Inherited Connections
• High Sigma Statistical Analysis Virtuoso Variation Option
• Advanced Statistical Analysis for Variation Aware Design
• Mismatch Contribution

Mixed-signal Verification:

• Low Power Mixed Signal Simulation
• SDF Annotation flow for AMS Simulations from Virtuoso ® ADE
• Mixed Signal Verification - Connectivity
• Modeling in Electrical, Wreal Verilog-AMS and SystemVerilog Electrical Equivalent

Methodology in Simulation:

• ADC Verification Workshop
• PLL Verification Workshop
• Crystal Oscillator Simulation using SpectreRF

Physical Implementation:

• Introduction to Connectivity-Driven Design in VLS XL
• IC 6.1.6 Constraint Driven Custom Design
• Virtuoso Floorplanner Flow
• IC 6.1.6 Rapid Analog Prototyping Workshop
• MODGEN
• IC6.1 Front to Back Overview
• Hierarchy Manipulation. Staying XL connectivity compliant when using Flatten, Make Cell and Transparent Instances
• Design Rule Driven (DRD) Editing and DRD Compactor
• Power, Ground and Structured Routing Implementation Flow

Physical Verification and Sign-off:

• Post-layout Extraction Flow: Using Black-Box-PVS LVS -> QRC Extraction Methodology
• Electrically Aware Design (EAD) Workshop
• Virtuoso IPVS
• Parasitic Aware Design Workshop
• Voltus-Fi EMIR Analysis Workshop

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