MEMS Design Contest

Cadence-Sponsored Training

Cadence offers Internet Learning Series (iLS) training that include dynamic course content, downloadable labs, instructor notes and bulletin boards.  These courses will help contest participants become familiar the Cadence MEMS and CMOS design software tools.  Courses are available to individuals that have access to the Cadence software platform. Additional iLS courses and workshops will be shown on this website in the future.

Cadence Online iLS Courses useful to MEMS Design Contest participants

Virtuoso Schematic Editor

In the Virtuoso®Schematic Editor course, you learn to create and edit schematics for use with the suite of Cadence® simulation and layout tools. You use the Verilog® In and SPICE In translators to generate netlists and symbols. You place instances, wire schematics, use hierarchical design, run netlist creation and simulation, add rules using the Constraint Editor, create inherited connections, open and use window assistants, and generate layout instances from the schematic.

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Virtuoso Analog Design Environment

This course introduces the Virtuoso® Analog Design Environment L for setting up and controlling analog and mixed-signal simulations. You run analog simulations using Spectre®, Spectre Turbo, and UltraSim simulators. You also explore our newest analog simulator, Accelerated Parallel Simulation (APS). You run specialized simulations, including device checking, DC match, Virtuoso Analog VoltageStorm® Option, and Virtuoso Analog ElectronStorm® Option. You apply the Open Command Environment for Analysis (OCEAN) scripting language to running simulations in a batch mode.

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Virtuoso Layout Design Basics

In this course, you learn the basic techniques for working with designs in the Virtuoso® Layout Suite L environment. You learn to create and edit cell-level designs and to create and place instances to build hierarchy for custom physical designs. You explore the basics of the user interface and the user-interface assistants, which help you select, navigate, search, highlight, edit, and create physical designs.

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Virtuoso Connectivity-Driven Layout Transition

This course guides the Virtuoso® Layout Suite L user into Virtuoso Layout Suite XL and GXL. You learn about the differences between the suites, about connectivity, and what drives the connectivity between the schematic and layout in XL/GXL. You are introduced to creating, modifying, and implementing constraints in the layout, and how to propagate them from the schematic. Included with this introduction, you explore Module Generators (ModGens) where interdigitation patterns of transistors, resistors, or capacitors can be set up either from the schematic or layout and treated as another constraint. Also, you are introduced to the Wire Editor and the Wire Assistant (only available in the XL and GXL suites), where you can define and implement design rule overrides any time.

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Virtuoso Layout Pro: T2 Create and Edit Commands (L)

In this course, you will learn how to use the advanced features introduced in Virtuoso® Layout Suite L. You will become familiar with commands to automate the creation of layout shapes and with commands which will improve the way you manage the objects in your design. You will also learn about the differences between paths and wires and how to take advantage of the wires in your everyday layout tasks.

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Virtuoso Layout Pro: T3 Basic Commands (XL)

This course focuses on the basic concepts required to work with Virtuoso® Layout Suite XL to create a layout using a connectivity-driven flow. You start with the creation and placement of your layout building blocks using manual and automated methods. You will learn about the Binder/Extractor, and also learn how to debug problems in the design connectivity. You will become familiar with Constraint Groups and learn how they affect your layout work.

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Virtuoso Layout Pro: T4 Advanced Commands (XL)

In this course, you analyze how to generate clones as free objects, grouped objects, and synchronized family. You use the Create Synchronous Copy feature, generate clones from modgen, create mutant clones, and analyze how to effectively reuse existing structures in your layout by using clone and copy. You create layout structures using features of the Generate Clones and Create Synchronous Copy commands. You update your layout after an Engineering Change Order (ECO) and update the layout to reflect the pin name changes between schematic and layout by using the Update Components and Nets (UCN) command. You use the Design-Rule-Driven (DRD) Editing and the DRD Interactive Compactor features in the Virtuoso® Layout Suite (XL).

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Virtuoso Layout Pro: T5 Interactive Routing (XL)

In this course, you explore techniques to increase your productivity using all the assisted features in the Create Wire family of commands in Virtuoso® Layout Suite XL. You use the different degrees of automation to route wires using the existing connectivity information. You use the smart auto via feature, and explore the Show Preview, and Show Hints options.

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Virtuoso Connectivity-Driven Layout

This course is the next step if you have already completed Virtuoso® Layout Design Basics. In this XL and GXL tier layout course, you implement the automation that connectivity-driven layout offers so you can attain first time silicon success. The course materials provide you with a comprehensive understanding of the power in the XL and GXL Virtuoso Layout Suites. You examine the Cadence® Help documents, the workspace design environment, and the new binder/extractor functionality while confirming connectivity between schematic and layout, implementing synchronous clones, and applying the Process Rules Editor to override existing design rules. You also place devices and pins and create interconnect by using the wire editor, point-to-point editor, and the guided routing editor. Using the space-based router, you autoroute a device-level design completely within the Virtuoso environment. You analyze and update data with an Engineering Change Order (ECO). By applying the Configure Physical Hierarchy tool, you examine and effect design changes. You also use the Module Generator to examine and create a module.

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Using Virtuoso Constraints Effectively

This course is a practical examination of the way to set specific rules in the schematic that will be transferred to the layout design. The specific rules are called constraints, which have more than just design rules available. The circuit prospector function searches for commonly understood configurations of devices or nets. When they are found, the designer can assign conditions that are passed to the layout, such as common centroids, matched parameters, symmetrical placement, or routing. There are a number of assistants, such as the Process Rules Editor, the Navigator, the Wire Assistant, and the Annotation Browser, all of which support passing the designers intent to the physical design. You can make changes in the layout that you can update back into the schematic. This course also describes validation and sign-off tools that examine and check any DRC or constraint violations as they occur rather than at the end of the design cycle where they cause.

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Switched Capacitor Circuit Simulation with Spectre and APS RF 

In this course, you get insights on how to simulate switched capacitor circuits using Spectre and APS RF. The training gives also valuable background information about the operation of switched capacitor circuits both in terms of noise behavior and frequency response. The recommended analysis methods are applied both to an elementary track/hold circuit and to a more complex C2V converter. 

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Verilog Language and Application

The Verilog Language and Application course offers a comprehensive exploration of the Verilog HDL and its application to ASIC and programmable logic design. The course provides a solid background in the use and application of the Verilog HDL to digital hardware design. This course covers all aspects of the language, from basic concepts and syntax through synthesis coding styles and guidelines to advanced language constructs and design verification. It also touches upon ASIC library design concepts.

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SystemVerilog for Design and Verification

This course gives you an in-depth introduction to the main SystemVerilog enhancements to the Verilog® hardware description language (HDL), discusses the benefits of the new features, and demonstrates how design and verification can be more efficient and effective when using SystemVerilog constructs.

The course breaks down into two modules. The Design module examines improvements for RTL design and synthesis; and the Verification module explores verification enhancements such as object-oriented design, assertions and randomization.

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Quantus QRC Transistor-Level T2: Parasitic Extraction

The course is designed to offer user-level experience on the next generation parasitic extraction solution from Cadence®– Quantus QRC. You explore the documentation system and Cadence® online support. You start with an overview of the PVS–Quantus QRC data flow and advance to hands-on extraction activities. You then set up the extraction environment in GUI mode or command line. You explore the considerations, settings and various features for Quantus parasitic extraction such as random walk field solver, adaptive meshing, split wide MOS or hierarchical extraction and then run multi-corner extraction with Quantus and perform Reduction Control & Advanced Virtual Metal Fill (VMF). Under specific extraction capabilities, you check out parasitic inductance extraction with PEEC – Wide Band Models and parasitic substrate extraction with Substrate Noise Analysis (SNA). In this course, you use the Virtuoso® Layout Suite. The Quantus QRC Extraction system is integrated into the Virtuoso menu bar for easy access.

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Advanced Statistical Analysis for Variation Aware Design

The Advanced Statistical Analysis for Variation Aware Design course outlines selected features included in Virtuoso Analog Design Environment (ADE) Assembler, Explorer and the Virtuoso Variation Option (VVO).  These tools are used to analyze a circuit, improve its performance, and investigate ways to estimate and improve the yield of a circuit.   Please email to obtain access to this course.


Design of a MEMS Accelerometer with the PCell Designer

Parameterized Cells (PCells) of devices are key elements used to increase flexibility and productivity during layout implementation of analog and mixed-signal designs. PCell Designer combines the ease of use of a graphical user interface (GUI) with a powerful object-oriented architecture for creation of reusable PCell classes and libraries. In this course you create a basic accelerometer (electrodes, spring, shuttle mass, anchor, top level cell) and then enhance the accelerometer by enhancing the electrodes, the spring and the shuttle mass. Additional enhancements include rounding the corners, creating rounded etch holes.  Please email to obtain access to this course.


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